With the increase in the possibility of incorporating multiple cores on a single chip (MCSoC), the issue of an efficient interconnection that is scalable, takes up small area and has low power consumption must be taken into consideration carefully. Network on chip (NoC) has evolved as a promising solution for efficiently interconnecting multiple core on a single chip (MCSoC). NoC brings conventional networking theories and methods to chip communication and brings notable improvements over the conventional bus systems.

The aim of my research will be to study power consumption in NoC architecture and propose an effective dynamic remapping algorithm to reduce power consumption on NoC. This is done by monitoring the NoC at run time and dynamically re-mapping the cores to reduce power consumption. Low power consumption is desirable in MCSoC because high power increases capacitance, electro magnetic interference (EMI) and dissipates more heat, thereby reducing performance. In addition, must devices built using MCSoC are hand-held devices (battery powered) and therefore might not have access to continuous power supply.

I will be using the OASIS NoC which was developed at the Adaptive systems laboratory, The University of Aizu, Graduate School of Computer Science and Engineering. Aizu, Japan To test my Algorithm. OASIS NoC is a complexity effective on-chip interconnection network.



Chapter I
1.0       Introduction
1.1       System on chip (SoC)
1.2       Multiprocessor System on chip (MPSoC)
1.3       Communication on MPSoC
1.4       Drawbacks of the conventional bus system
1.5       Network-on-chip (NoC)
1.6       Properties of NoC
            1.6.1.   Network Topology
            1.6.2.   Switching Scheme
            1.6.3.   Flow Control
            1.6.4.   Packet Format
            1.6.5.   Queuing Scheme
            1.6.6.   Routing Scheme
1.7 NoC Design Flow
1.8 OASIS Network on Chip (NoC)

Chapter II
2.0 Objective of the Research
2.2       Energy model of NoC
2.3       Causes and Types of power consumption on NoCs
            2.3.1.   The router or Switch fabric
            2.3.2.   Buffers on Router
            2.3.3.   Link Length
            2.3.4.   Size of flits
            2.3.5.   Routing Protocol
2.4       Desirability of Low Power
2.5       Advantages of the Adaptive NoC over the Application-specific NoC
2.6       Power Management Policies and Methods
            2.6.1.   Reconfigurable buffers/routers
            2.6.2.   Multi-Mode Switch
            2.6.3.   Dynamic Voltage scaling Closed-loop control concept
            2.6.4.   Voltage island shut-down
            2.6.5.   Reconfigurable Architecture
            2.6.6.   Reconfigurable Topology
2.7       Why Dynamic Re-mapping?
2.8       NoC Monitoring
2.8.1  Probe Architecture

Chapter III
3.0       Application Mapping
3.1       Static Mapping
3.2       Dynamic Mapping
3.3       Dynamic Re-Mapping Algorithm
            3.3.1.   The Algorithm
            3.3.2.   Algorithm Discussion

Chapter IV
4.0       Problem Statement
4.1       Simulation Set up and Algorithm Implementation (Case Study)
4.2       Validation of Result and Performance Evaluation and Conclusion
            4.2.1.   The Lookup Table
            4.2.2.   Selecting The Root
            4.2.3.   Selecting Neighbours of the Root
            4.2.4.   Selecting Neighbours of the Neighbours
4.3       Conclusion and Future Work

Chapter I

1.0 Introduction

For the next decade, Moore’s Law is still going to bring higher transistor densities allowing billions of transistors to be integrated on a single chip. However, it became obvious that exploiting significant amounts of instruction-level parallelism with deeper pipelines and more aggressive wide-issue super-scalar techniques, and using most of the transistor budget for large on-chip caches has come to a dead end. Scaling performance with higher clock frequencies, especially, is getting more and more difficult because of heat dissipation problems and energy consumption that is too high. The latter is not only a technical problem for mobile systems, but is also becoming a severe problem for computing centres because high energy consumption leads to significant cost factors in the budget. Improving performance can only be achieved by exploiting parallelism on all system levels [1].

Multicore architectures offer a better performance/Watt ratio than single-core architectures with similar performance. Combining multi-core and co-processor technology promise extreme computing power for high CPU-time-consuming applications. [1]

1.1 System on chip (SoC):

System-on-a-chip or system on chip (SoC or SOC) refers to integrating all components of a computer or other electronic system into a single integrated circuit (chip). It may contain digital, analogue, mixed-signal, and often radio-frequency functions – all on a single chip substrate. A typical application is in the area of embedded systems....

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