DESIGN AND EVALUATION OF AN ADAPTIVE NETWORK ON CHIP FOR MULTICORE ARCHITECTURES

ABSTRACT
Network – On – Chip (NoC) communication architecture have emerged as a solution to problem of lack of scalability, clock delay, lack of support for concurrent communication and power consumption exhibited by the shared bus communication approach to System - On - Chip (SoC) implementations. However, a NoC communication requirement such as bandwidth is affected by architecture parameters as topology, routing, buffer size etc.

In this project, we implement an adaptive approach of NoC to solve the problems of the static approach method such as routing delay, lack of flexibility and inability to predict dynamic behaviour of the applications. The adaptive approach supports several applications by changing parameters at run – time.


TABLE OF CONTENTS

Abstract
Table of Contents

Chapter 1: Introduction
1.1       Introduction to System On Chip
1.2       Emergence of Network On Chip (NOC)
1.3       Related Work
1.4       Problems of NOC
1.4.1    Topology
1.4.2    Buffer Size
1.4.3    Channel Width
1.4.4    Routing
1.5       Project Contribution
1.6       Report Organization

Chapter 2: Network On Chip
2.1       Introduction
2.2       On – Chip System Interconnection Overview
2.2.1    Bus – Based System
2.2.2    The NOC – Based
2.2.3    NOC Designs Issues

Chapter 3: OASIS Interconnection Network
3.1       Introduction
3.2       OASIS NoC Architecture
3.2.1    Switching
3.2.2    Routing
3.2.3    Flow Control

Chapter 4: OASIS With Run Time Monitoring System
4.1       Introduction
4.2       Algorithm
4.2.1    Routing
4.2.2    Switching
4.3       Architecture
4.3.1    Algorithm Implementation in Hardware

Chapter 5: Hardware and Software Evaluation Results
5.1       Hardware Complexity
5.1.1    Logic
5.1.2    Power
5.1.3    Speed
5.2       Functional Simulation
5.2.1    Algorithm Verification
5.2.2    Packet Delay

Chapter 6: CONCLUSION
REFERENCES


Chapter 1 : Introduction


1.1  Introduction to System On Chip

Complex applications, using System On Chips (SoCs) can be implemented by integrating more cores since the number of cores increases rapidly. That is, the rapid development of cores technology allows complex circuits to be integrated into a single chip. This also means that the system's complexity also increases; hence designers tend to keep up with the increased complexity by using larger reusable blocks in their system design.

However, with these different processing elements used together to achieve powerful systems, connecting these cores together posses a great challenge. And as the number of these computational units/processing units increases and are integrated into one silicon chip, communication between them becomes a problem. A communication system that will support these cores must be designed.

Bus – based communication, where bus access request of nodes or cores are serialized through central arbiters, is a simple solution to the communication problem. However, this simple approach presents numerous challenges like scalability problem, bus capacitance increases dramatically with increase bus length and more additional cores, performance penalties, inefficient power or energy as the number of cores increases.


1.2  Emergence of Network On Chip (NOC)
NoC is a concept of communication in System on Chips (SoCs) [6,]. This concept claims to eliminate the problems of the Bus – based communication highlighted above. Unlike Bus – based communication where communication is done through buses and dedicated point-to-point links, Network On Chip, NoC, a more general scheme is adapted, employing a grid of routing nodes spread out across the chip, connected by communication links. The NoC design paradigm is centred communication rather than computation [4]. Each node (or tile) in the on-chip network is composed of a Processing Element (PE) and a communication unit which is so called.....

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Item Type: Postgraduate Material  |  Attribute: 49 pages  |  Chapters: 1-5
Format: MS Word  |  Price: N3,000  |  Delivery: Within 30Mins.
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